A dynamic-type semiconductor-memory device (DRAM) comprises a plurality of memory cells, each of which has one transistor and one capacitor, and which occupies a small area. In a DRAM, information is recorded by storing data in the capacitor, so due to leak current, charge stored in the memory cell decreases over time. Therefore, before the stored information is lost, it is necessary to perform a refresh operation in which the information stored in a memory cell is read by a sense amplifier, and then the read data is restored to the memory cell by that sense amplifier. On the other hand, a static-type semiconductor-memory device (SRAM) comprises a plurality of memory cells, each of which is composed by a flip-flop. In a SRAM, a refresh operation is not necessary, however, one memory cell is consisted of four transistors and two load elements, for example, so the area occupied by the memory cell is larger than that of a DRAM, and the chip size of a large capacity SRAM becomes large.
Recently, there has been developed and manufactured such a memory device adapted to high-storage capacity and high-speed application in a portable terminal or the like, that includes dynamic-type memory cells, has input/output interface, for example, compliant with asynchronous-type SRAM specifications (called a pseudo SRAM) and performs hidden refresh operation that does not require refresh control from the outside (see Non-Patent Document 1).
In a typical general-purpose DRAM, refresh control is performed from an external controller, and control is performed such that in an active state, refresh operation is performed under the control from the outside by an interrupt or the like, while in a standby state, the refresh operation is performed periodically under the control from the outside. On the other hand, in the case of a typical pseudo SRAM, in an active state, hidden refresh is used that is triggered by a time out of a built-in timer, for example, and generally refresh control is not performed under the control from the outside, also in a standby state, self refresh is performed. Regardless of whether or not being used for a portable terminal, in a semiconductor-memory device (DRAM), standby control is performed in order to keep power consumption low.
FIG. 5 is a schematic diagram showing an example of a typical conventional DRAM (for example, pseudo SRAM) that has a self-refresh function. Referring to FIG. 5, the DRAM comprises: a memory core 100 including DRAM cells; a row decoder (X decoder) 101 that functions as an address decoder and has a word driver (not shown) that decodes a row address and drives a selected word line; a sense amplifier 102 that senses memory data read on a bit line associated with a selected memory cell (not shown) in the memory core 100, and writes data to a selected memory cell; and a column decoder (Y decoded) 103 that decodes a column address and turns on a selected Y switch (not shown) to connect a bit line to an I/O bus. DRAM cells are arranged in an array format in which at points where each of a plurality of word lines intersects a plurality of bit lines. The DRAM cell comprises a capacitor and a MOS transistor, a gate which is connected to the word line, and one of source and drain of which is connected to the bit line, and the other of source and drain of which is connected to the capacitor. The DRAM further comprises a data-input/output controller 104, address-buffer latches 105A and 105B, multiplexer 106, counter 107, timer 108, refresh-control circuit 109, timing-control circuit 110, read/write-control circuit 111, input buffer 112 and output buffer 113.
The data-input/output controller 104 controls switching between sending write data to be written to the memory core 100 and receiving read data read from the memory core 100. The address-buffer latch 105A receives and latches a row address ROWAdd from an address terminal Add. The address-buffer latch 105B receives and latches a column address COLAdd from an address terminal Add. The latch timing of the address-buffer latches 105A and 105B can be when an address-valid signal not shown (signal that indicates that the address signal on an address bus is valid) is activated. The row address ROWAdd output from the address-buffer latch 105A is supplied to one of the input terminals of the multiplexer 106, and the refresh address REFAdd from the counter 107 is supplied to the other input terminal during refresh. The multiplexer 106 receives a refresh-control signal φ REF from the refresh-control circuit 109 as a selection-control signal, and during refresh, selects the refresh address REFAdd and supplies it to the row decoder 101, and at all other times, selects the row address ROWAdd from the address-buffer latch 105A and supplies it to the row decoder 101.
In a standby state, the refresh-control circuit 109 performs control such that the counter 107 counts up responsive to a trigger signal (REFREQ; trigger signal for requesting a refresh) that is generated each time when timeout occurs in a timer 108, and the output from the counter 107 is supplied to the multiplexer 106 as the refresh address REFAdd. In an active state, the refresh-control circuit 109 carries out hidden refresh that does not require refresh control from the outside. In hidden refresh, when the refresh operation invoked by the timeout in the timer 108 occurs at the same time as read/write access for example, the refresh-control circuit 109 performs control causing read/write access to wait until the refresh operation has been completed, or any other control methods for performing refreshing automatically may be used. One of other method is such that when a predetermined time has elapsed after read/write access, refreshing is carried out automatically. The read/write-control circuit 111 receives a write-enable signal /WE, and chip-select signal /CS and performs read/write control. The timing-control circuit 110 receives the refresh-control signal φ REF from the refresh-control circuit 109, and a read/write-control signal R/W for and controlling read/write operation output from the read/write-control circuit 111 and supplies to the row decoder 101 a strobe signal φ RS for stipulating an activation period of a selected word line driven by a word driver (not shown) provided in the row decoder 101. The write data from a data terminal Data is supplied to the data-input/output controller 104 via the input buffer 112, and is written in the selected cell of the memory core 100. Read data that has been read from the selected cell is output from the data-input/output controller 104 to the data terminal Data via the output buffer 113. The output buffer 113 is activated when the output-enable signal /OE is at a low level, while when the output-enable signal /OE is at a high level, the output of the output buffer 113 is set in a high-impedance state. In FIG. 5, ‘/’ provided in front of a signal name (terminal name) such as /CS, /WE and /OE indicates that the active state thereof is when the level of the signal is at a low level (low active). Construction is also possible in which there is a standby-control circuit (not shown) that receives the chip-select signal /CS and performs standby control of the memory core 100.
FIG. 6 is a diagram illustrating an example of operation when the semiconductor-memory device shown in FIG. 5 changes from the standby state to the active state. As the read/write command, the chip-select signal /CS and the write-enable signal /WE may be used in such a way wherein a read operation may be performed when the chip-select signal /CS is low, and the write-enable signal /WE is high, while a write operation may be performed when the chip-select signal /CS is low, and the write-enable signal /WE is low. The other configuration may be such that a command is supplied to a command decoder (not shown) and based on the decoded result from that command decoder, a signal is generated that control read/write access.
As shown in FIG. 6, in the conventional semiconductor-memory device shown in FIG. 5, if, at the time of the transition from the standby state to the active state, which is invoked by an access request, the refresh operation that was started in the standby state continues to be performed, it is necessary to perform control so that the read/write access is delayed until that refresh operation ends.
In the Patent Document 1, the configuration of a DRAM that is as easy to use as an SRAM is disclosed in which the DRAM comprises an auto-refresh circuit that detects the timing of change in an address signal, and generates all timing required for the write, read and refresh operations, simplifies timing control from the outside, and performs self refresh and auto refresh of dynamic-type memory cells according to address signal that are formed internally according to an external refresh signal.
Also, as a pseudo SRAM, in the Patent Document 2, there is disclosed a DRAM having an interface that is SRAM compatible and that performs hidden refresh that is capable of completely hiding refresh operation from the outside.    [Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-59-52495 (FIG. 1)    [Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2003-123470A (FIG. 1)    [Non-patent Document 1]
NEC Electronics—Product Lineup, Mobile RAM, Nov. 17, 2004 Internet search <URL: http://www.necel.com/memory/Japanese/products/msram/info.html/>